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Si4313-B1
First Bit
Last Bit
SDI
RW
=0
A6 A5 A4 A3 A2 A1 A0
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
SCLK
First Bit
Last Bit
SDO
D7 D6 D5 D4 D3
D2 D1 D0
nSEL
Figure 3. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode, which allows for reading/writing sequential registers without
having to resend the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An example burst write
transaction is shown in Figure 4, and a burst read is shown in Figure 5. As long as nSEL is held low, input data will
be latched into the Si4313 every eight SCLK cycles.
First Bit
Last Bit
SDI
RW
=1
A6 A5 A4 A3 A2 A1 A0
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
SCLK
nSEL
Figure 4. SPI timing—Burst Write Mode
First Bit
Last Bit
SDI
RW
=0
A6 A5 A4 A3 A2 A1 A0
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
SCLK
First Bit
SDO
D7 D6 D5 D4 D3
D2 D1 D0 D7 D6 D5 D4 D3
D2 D1 D0
nSEL
Figure 5. SPI timing—Burst Read Mode
18
Rev. 1.0
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